纳米MOSFET迁移率解析模型

从玻尔兹曼方程出发，重新计算了纳米MOSFET沟道内的载流子所服从的分布函数，特别是考虑了纳米MOSFET横向电场和纵向电场之间的相互作用，并且以得到的非平衡状态下的分布函数为基础，考虑载流子寿命和速度的统计分布，给出了纳米MOSFET载流子迁移率的解析表达式.通过与数值模拟结果进行比较和分析，该迁移率解析模型形式简洁、物理概念清晰，且具有相当精度. 关键词： 玻尔兹曼方程 纳米MOSFET 迁移率 沟道有效电场     

Membrane-oxide semiconductor field-effect transistor (MOSFET) sensors

MOSFET-sensors can be considered as membrane-oxide-semiconductor field-effect transistors. MOSFETs can be divided into ISFETs, GasFETs, BioFETs, these sensors being sensitive to ion, gas, biomolecules respectively and there is also a possibility to fabricate MOSFET reference electrode (RefFET). The development and theoretical treatment of various type of MOSFET-sensors are presented in this paper.     

Effect of gate engineering in JLSRG MOSFET to suppress SCEs: An analytical study

In this work, an analytical model of gate-engineered junctionless surrounding gate MOSFET (JLSRG) has been proposed to uncover its potential benefit to suppress short-channel effects (SCEs). Analytical modelling of centre potential for gate-engineered JLSRG devices has been developed using parabolic approximation method. From the developed centre potential, the parameters like threshold voltage, surface potential, Electric Field, Drain-induced Barrier Lowering (DIBL) and subthershold swing are determined. A nice agreement between the results obtained from the model and TCAD simulation demonstrates the validity and correctness of the model. A comparative study of the efficacy to suppress SCEs for Dual-Material (DM) and Single-Material (SM) junctionless surrounding gate MOSFET of the same dimensions has also been carried out. Result indicates that TM-JLSRG devices offer a noticeable enhancement in the efficacy to suppress SCEs by as compared to SM-JLSRG and DM-JLSRG device structures. The effect of different length ratios of three channel regions related to three different gate materials of TM-JLSRG structure on the SCEs have also been discussed. As a result, we demonstrate that TM-JLSRG device can be considered as a competitive contender to the deep-submicron mainstream MOSFETs for low-power VLSI applications.     

Investigation of laterally single-diffused metal oxide semiconductor (LSMOS) field effect transistor

We propose a distinct approach to implement a laterally single diffused metal-oxide-semiconductor (LSMOS) FET with only one impurity doped p-n junction. In the LSMOS, a single p-n junction is first created using lateral dopant diffusion. The channel is formed in the p region of the p-n junction and the n region acts as the drift region. Two distinct metals of different work function are used to form the “n⁺” source/drain regions and “p⁺” body contact using the charge plasma concept. We demonstrate that the LSMOS is similar in performance to a laterally double diffused metal-oxide-semiconductor (LDMOS) although it has only one impurity doped p-n junction. The LSMOS exhibits a breakdown voltage of ∼50.0 V, an average ON-resistance of 48.7 mΩ-mm² and a peak transconductance of 53.6 μS/μm similar to that of a comparable LDMOS.     

3D analysis of in-filled trench as passive barriers for ground vibration isolation

The three-dimensional (3D) problem of the ground vibration isolation by an in-filled trench as a passive barrier is studied theoretically. Integral equations governing Rayleigh wave scattering are derived based on the Green’s solution of Lamb problem. The integral equations are solved accurately and efficiently with an iteration technique. They are used to evaluate the complicated Rayleigh wave field generated by irregular scatterers embedded in an elastic half-space solid. The passive isolation effectiveness of ground vibration by the in-filled trench for screening Rayleigh wave is further studied in detail. Effects of relevant parameters on the effectiveness of vibration isolation are investigated and presented. The results show that a trench filled with stiff backfill material gets a better isolation effect than a soft one, and increasing the depth or width of the in-filled trench also improves its screening effectiveness. The effectiveness and the area of the screened zone are surging with the increase in the length of the in-filled trench. Supported by the National Natural Science Foundation of China (Grant Nos. 50678128 and 50538010) and the Research Fund for PhD Student of Chinese College (Grant No. 20050247030)     

MOSFET调制器的实验研究

 介绍了MOSFET调制器的基本原理，并对其并联分流和感应叠加两种开关结构进行了实验研究。基于可编辑逻辑器件设计了其触发电路，驱动电路采用高速MOSFET对管组成的推挽输出形式，加快了MOSFET的开关速度。利用Pspice软件对开关上有无剩余电流电路(RCD)两种情况进行仿真，结果表明，加装RCD电路可以有效吸收MOSFET在关断瞬间产生的反峰电压。实验中，电流波形用Pearson线圈测量，用3个MOSFET并联作开关，当电容充电电压为450 V，负载为30 Ω时，脉冲电流13 A，前沿20 ns，平顶约80 ns；用3个单元调制器感应叠加，当电容充电电压为450 A，负载为30 Ω时，脉冲电流强度为40 A，前沿25 ns，平顶约70 ns。     

Effect of interface-roughness scattering on mobility degradation in SiGe p-MOSFETs with a high-k dielectric/SiO2 gate stack＊

A physical model for mobility degradation by interface-roughness scattering and Coulomb scattering is proposed for SiGe p-MOSFET with a high-k dielectric/SiO2 gate stack. Impacts of the two kinds of scatterings on mobility degradation are investigated. Effects of interlayer （SiO2） thickness and permittivities of the high-k dielectric and interlayer on carrier mobility are also discussed. It is shown that a smooth interface between high-k dielectric and interlayer, as well as moderate permittivities of high-k dielectrics, is highly desired to improve carriers mobility while keeping alow equivalent oxide thickness. Simulated results agree reasonably with experimental data.     

Magnetoconductivity of Hubbard bands induced in silicon MOSFETs

Sodium impurities are diffused electrically to the oxide-semiconductor interface of a silicon MOSFET to create an impurity band. At low temperature and at low electron density, the band is split into an upper and a lower sections under the influence of Coulomb interactions. We used magnetoconductivity measurements to provide evidence for the existence of Hubbard bands and determine the nature of the states in each band.     

A threshold voltage model MOSFETs considering for high-k gate-dielectric fringing-field effect

In this paper, a threshold voltage model for high-k gate-dielectric metal-oxide-semiconductor field-effect transistors （MOSFETs） is developed, with more accurate boundary conditions of the gate dielectric derived through a conformal mapping transformation method to consider the fringing-field effects including the influences of high-k gate-dielectric and sidewall spacer. Comparing with similar models, the proposed model can be applied to general situations where the gate dielectric and sidewall spacer can have different dielectric constants. The influences of sidewall spacer and high-k gate dielectric on fringing field distribution of the gate dielectric and thus threshold voltage behaviours of a MOSFET are discussed in detail.     

Interface control of high-k gate dielectrics on Ge

Important progress has been made in the passivation of Ge/gate dielectric interfaces. One important approach is by thermally oxidized GeO₂ interface and ALD high-k layers, with an interface state density D_it ∼ 2 × 10¹¹ cm⁻² eV⁻¹. Another approach is with an epi-Si/SiO₂ interface, resulting in similar D_it. Hysteresis and V_th shift, however, are still not optimal. Extensive material characterization and theoretical insights help us understanding the root cause of these remaining issues and show the way to improved interface control.